cc2530_user_guide下载

Preface....................................................................................................................................... 14 1 Introduction ....................................................................................................................... 17 1.1 Overview..................................................................................................................... 18 1.1.1 CPU and Memory ................................................................................................. 21 1.1.2 Clocks and Power Management ................................................................................ 21 1.1.3 Peripherals ......................................................................................................... 21 1.1.4 Radio................................................................................................................ 23 1.2 Applications ................................................................................................................. 23 2 8051 CPU........................................................................................................................... 24 2.1 8051 CPU Introduction .................................................................................................... 25 2.2 Memory ...................................................................................................................... 25 2.2.1 Memory Map ....................................................................................................... 25 2.2.2 CPU Memory Space .............................................................................................. 27 2.2.3 Physical Memory .................................................................................................. 28 2.2.4 XDATA Memory Access.......................................................................................... 33 2.2.5 Memory Arbiter .................................................................................................... 33 2.3 CPU Registers .............................................................................................................. 34 2.3.1 Data Pointers ...................................................................................................... 34 2.3.2 Registers R0–R7 .................................................................................................. 35 2.3.3 Program Status Word............................................................................................. 35 2.3.4 Accumulator........................................................................................................ 36 2.3.5 B Register .......................................................................................................... 36 2.3.6 Stack Pointer....................................................................................................... 36 2.4 Instruction Set Summary .................................................................................................. 36 2.5 Interrupts .................................................................................................................... 40 2.5.1 Interrupt Masking .................................................................................................. 41 2.5.2 Interrupt Processing............................................................................................... 45 2.5.3 Interrupt Priority.................................................................................................... 47 3 Debug Interface.................................................................................................................. 50 3.1 Debug Mode ................................................................................................................ 51 3.2 Debug Communication .................................................................................................... 51 3.3 Debug Commands ......................................................................................................... 53 3.3.1 Debug Configuration .............................................................................................. 55 3.3.2 Debug Status ...................................................................................................... 55 3.3.3 Hardware Breakpoints ............................................................................................ 56 3.4 Flash Programming ........................................................................................................ 57 3.4.1 Lock Bits............................................................................................................ 57 3.5 Debug Interface and Power Modes...................................................................................... 57 3.6 Registers .................................................................................................................... 59 4 Power Management and Clocks ........................................................................................... 60 4.1 Power Management Introduction......................................................................................... 61 4.1.1 Active and Idle Modes ............................................................................................ 62 4.1.2 PM1 ................................................................................................................. 62 4.1.3 PM2 ................................................................................................................. 62 4.1.4 PM3 ................................................................................................................. 62 4.2 Power-Management Control .............................................................................................. 62 4.3 Power-Management Registers ........................................................................................... 63 4.4 Oscillators and Clocks ..................................................................................................... 66 4.4.1 Oscillators .......................................................................................................... 66 4.4.2 System Clock ...................................................................................................... 66 4.4.3 32-kHz Oscillators ................................................................................................. 67 4.4.4 Oscillator and Clock Registers .................................................................................. 67 4.5 Timer Tick Generation ..................................................................................................... 69 4.6 Data Retention.............................................................................................................. 69 5 Reset ................................................................................................................................ 70 5.1 Power-On Reset and Brownout Detector ............................................................................... 71 5.2 Clock-Loss Detector ....................................................................................................... 71 6 Flash Controller ................................................................................................................. 72 6.1 Flash Memory Organization............................................................................................... 73 6.2 Flash Write .................................................................................................................. 73 6.2.1 Flash-Write Procedure............................................................................................ 73 6.2.2 Writing Multiple Times to a Word ............................................................................... 74 6.2.3 DMA Flash Write .................................................................................................. 74 6.2.4 CPU Flash Write................................................................................................... 75 6.3 Flash Page Erase .......................................................................................................... 75 6.3.1 Performing Flash Erase From Flash Memory ................................................................. 76 6.3.2 Different Flash Page Size on CC2533 ......................................................................... 76 6.4 Flash DMA Trigger ......................................................................................................... 76 6.5 Flash Controller Registers ................................................................................................ 76 7 I/O Ports............................................................................................................................ 78 7.1 Unused I/O Pins ............................................................................................................ 79 7.2 Low I/O Supply Voltage ................................................................................................... 79 7.3 General-Purpose I/O ....................................................................................................... 79 7.4 General-Purpose I/O Interrupts........................................................................................... 79 7.5 General-Purpose I/O DMA ................................................................................................ 80 7.6 Peripheral I/O ............................................................................................................... 80 7.6.1 Timer 1.............................................................................................................. 81 7.6.2 Timer 3.............................................................................................................. 81 7.6.3 Timer 4.............................................................................................................. 82 7.6.4 USART 0 ........................................................................................................... 82 7.6.5 USART 1 ........................................................................................................... 82 7.6.6 ADC ................................................................................................................. 83 7.6.7 Operational Amplifier and Analog Comparator ................................................................ 83 7.7 Debug Interface............................................................................................................. 83 7.8 32-kHz XOSC Input ........................................................................................................ 83 7.9 Radio Test Output Signals ................................................................................................ 84 7.10 Power-Down Signal MUX (PMUX)....................................................................................... 84 7.11 I/O Registers ................................................................................................................ 84 8 DMA Controller .................................................................................................................. 92 8.1 DMA Operation ............................................................................................................. 93 8.2 DMA Configuration Parameters .......................................................................................... 95 8.2.1 Source Address.................................................................................................... 95 8.2.2 Destination Address............................................................................................... 95 8.2.3 Transfer Count..................................................................................................... 95 8.2.4 VLEN Setting....................................................................................................... 96 8.2.5 Trigger Event....................................................................................................... 96 8.2.6 Source and Destination Increment.............................................................................. 96 8.2.7 DMA Transfer Mode .............................................................................................. 97 8.2.8 DMA Priority........................................................................................................ 97 8.2.9 Byte or Word Transfers........................................................................................... 97 8.2.10 Interrupt Mask .................................................................................................... 97 8.2.11 Mode 8 Setting ................................................................................................... 97 8.3 DMA Configuration Setup ................................................................................................. 97 8.4 Stopping DMA Transfers .................................................................................................. 98 8.5 DMA Interrupts.............................................................................................................. 98 8.6 DMA Configuration-Data Structure....................................................................................... 98 8.7 DMA Memory Access...................................................................................................... 98 8.8 DMA Registers ............................................................................................................ 101 9 Timer 1 (16-Bit Timer)........................................................................................................ 103 9.1 16-Bit Counter............................................................................................................. 104 9.2 Timer 1 Operation ........................................................................................................ 104 9.3 Free-Running Mode ...................................................................................................... 104 9.4 Modulo Mode.............................................................................................................. 105 9.5 Up-and-Down Mode ...................................................................................................... 105 9.6 Channel-Mode Control ................................................................................................... 105 9.7 Input Capture Mode ...................................................................................................... 106 9.8 Output Compare Mode................................................................................................... 106 9.9 IR Signal Generation and Learning .................................................................................... 111 9.9.1 Introduction ....................................................................................................... 111 9.9.2 Modulated Codes ................................................................................................ 111 9.9.3 Non-Modulated Codes .......................................................................................... 112 9.9.4 Learning........................................................................................................... 113 9.9.5 Other Considerations............................................................................................ 113 9.10 Timer 1 Interrupts ......................................................................................................... 113 9.11 Timer 1 DMA Triggers.................................................................................................... 113 9.12 Timer 1 Registers ......................................................................................................... 114 9.13 Accessing Timer 1 Registers as Array ................................................................................ 119 10 Timer 3 and Timer 4 (8-Bit Timers)...................................................................................... 120 10.1 8-Bit Timer Counter....................................................................................................... 121 10.2 Timer 3 and Timer 4 Mode Control..................................................................................... 121 10.2.1 Free-Running Mode ............................................................................................ 121 10.2.2 Down Mode...................................................................................................... 121 10.2.3 Modulo Mode.................................................................................................... 121 10.2.4 Up-and-Down Mode ............................................................................................ 121 10.3 Channel Mode Control ................................................................................................... 121 10.4 Input Capture Mode ...................................................................................................... 122 10.5 Output Compare Mode................................................................................................... 122 10.6 Timer 3 and Timer 4 Interrupts.......................................................................................... 122 10.7 Timer 3 and Timer 4 DMA Triggers .................................................................................... 123 10.8 Timer 3 and Timer 4 Registers.......................................................................................... 123 11 Sleep Timer...................................................................................................................... 128 11.1 General..................................................................................................................... 129 11.2 Timer Compare ........................................................................................................... 129 11.3 Timer Capture ............................................................................................................. 129 11.4 Sleep Timer Registers ................................................................................................... 130 12 ADC ................................................................................................................................ 132 12.1 ADC Introduction.......................................................................................................... 133 12.2 ADC Operation ............................................................................................................ 133 12.2.1 ADC Inputs ...................................................................................................... 133 12.2.2 ADC Conversion Sequences.................................................................................. 134 12.2.3 Single ADC Conversion........................................................................................ 134 12.2.4 ADC Operating Modes ......................................................................................... 134 12.2.5 ADC Conversion Results ...................................................................................... 135 12.2.6 ADC Reference Voltage ....................................................................................... 135 12.2.7 ADC Conversion Timing ....................................................................................... 135 12.2.8 ADC Interrupts .................................................................................................. 135 12.2.9 ADC DMA Triggers ............................................................................................. 135 12.2.10 ADC Registers................................................................................................. 136 13 Battery Monitor ................................................................................................................ 139 13.1 Functionality and Usage of the Battery Monitor ...................................................................... 140 13.2 Using the Battery Monitor for Temperature Monitoring .............................................................. 140 13.3 Battery Monitor Registers ............................................................................................... 141 14 Random-Number Generator ............................................................................................... 143 14.1 Introduction ................................................................................................................ 144 14.2 Random-Number-Generator Operation ................................................................................ 144 14.2.1 Pseudorandom Sequence Generation....................................................................... 144 14.2.2 Seeding .......................................................................................................... 144 14.2.3 CRC16 ........................................................................................................... 144 14.3 Random-Number-Generator Registers ................................................................................ 145 15 AES Coprocessor ............................................................................................................. 146 15.1 AES Operation ............................................................................................................ 147 15.2 Key and IV ................................................................................................................. 147 15.3 Padding of Input Data .................................................................................................... 147 15.4 Interface to CPU .......................................................................................................... 147 15.5 Modes of Operation ...................................................................................................... 147 15.6 CBC-MAC.................................................................................................................. 147 15.7 CCM Mode................................................................................................................. 148 15.8 AES Interrupts............................................................................................................. 150 15.9 AES DMA Triggers ....................................................................................................... 150 15.10 AES Registers ............................................................................................................ 150 16 Watchdog Timer ............................................................................................................... 152 16.1 Watchdog Mode........................................................................................................... 153 16.2 Timer Mode................................................................................................................ 153 16.3 Watchdog Timer Register................................................................................................ 153 17 USART ............................................................................................................................ 155 17.1 UART Mode ............................................................................................................... 156 17.1.1 UART Transmit.................................................................................................. 156 17.1.2 UART Receive .................................................................................................. 156 17.1.3 UART Hardware Flow Control ................................................................................ 156 17.1.4 UART Character Format....................................................................................... 157 17.2 SPI Mode .................................................................................................................. 157 17.2.1 SPI Master Operation .......................................................................................... 157 17.2.2 SPI Slave Operation............................................................................................ 158 17.3 SSN Slave-Select Pin .................................................................................................... 158 17.4 Baud-Rate Generation ................................................................................................... 158 17.5 USART Flushing .......................................................................................................... 159 17.6 USART Interrupts ......................................................................................................... 159 17.7 USART DMA Triggers.................................................................................................... 159 17.8 USART Registers ......................................................................................................... 159 18 Operational Amplifier ........................................................................................................ 164 18.1 Description................................................................................................................. 165 18.2 Calibration ................................................................................................................. 165 18.3 Clock Source .............................................................................................................. 165 18.4 Registers ................................................................................................................... 165 19 Analog Comparator........................................................................................................... 166 19.1 Description................................................................................................................. 167 19.2 Register .................................................................................................................... 167 20 I2C................................................................................................................................... 168 20.1 Operation .................................................................................................................. 169 20.1.1 I2C Initialization and Reset..................................................................................... 170 20.1.2 I2C Serial Data .................................................................................................. 170 20.1.3 I2C Addressing Modes ......................................................................................... 171 20.1.4 I2C Module Operating Modes ................................................................................. 171 20.1.5 I2C Clock Generation and Synchronization.................................................................. 177 20.1.6 Bus Error......................................................................................................... 178 20.1.7 I2C Interrupt ...................................................................................................... 178 20.1.8 I2C Pins........................................................................................................... 178 20.2 I2C Registers............................................................................................................... 178 21 USB Controller ................................................................................................................. 181 21.1 USB Introduction .......................................................................................................... 182 21.2 USB Enable................................................................................................................ 182 21.3 48-MHz USB PLL......................................................................................................... 182 21.4 USB Interrupts............................................................................................................. 183 21.5 Endpoint 0 ................................................................................................................. 183 21.6 Endpoint-0 Interrupts ..................................................................................................... 183 21.6.1 Error Conditions................................................................................................. 184 21.6.2 SETUP Transactions (IDLE State) ........................................................................... 184 21.6.3 IN Transactions (TX State) .................................................................................... 184 21.6.4 OUT Transactions (RX State)................................................................................. 185 21.7 Endpoints 1–5 ............................................................................................................. 185 21.7.1 FIFO Management ............................................................................................. 185 21.7.2 Double Buffering ................................................................................................ 186 21.7.3 FIFO Access..................................................................................................... 187 21.7.4 Endpoint 1–5 Interrupts ........................................................................................ 187 21.7.5 Bulk or Interrupt IN Endpoint .................................................................................. 188 21.7.6 Isochronous IN Endpoint....................................................................................... 188 21.7.7 Bulk or Interrupt OUT Endpoint ............................................................................... 188 21.7.8 Isochronous OUT Endpoint.................................................................................... 188 21.8 DMA ........................................................................................................................ 189 21.9 USB Reset ................................................................................................................. 189 21.10 Suspend and Resume ................................................................................................... 189 21.11 Remote Wake-Up ........................................................................................................ 189 21.12 USB Registers ............................................................................................................ 190 22 Timer 2 (MAC Timer) ......................................................................................................... 197 22.1 Timer Operation........................................................................................................... 198 22.1.1 General........................................................................................................... 198 22.1.2 Up Counter ...................................................................................................... 198 22.1.3 Timer Overflow.................................................................................................. 198 22.1.4 Timer Delta Increment ......................................................................................... 198 22.1.5 Timer Compare ................................................................................................. 198 22.1.6 Overflow Count.................................................................................................. 198 22.1.7 Overflow-Count Update ........................................................................................ 199 22.1.8 Overflow-Count Overflow ...................................................................................... 199 22.1.9 Overflow-Count Compare...................................................................................... 199 22.1.10 Capture Input .................................................................................................. 199 22.1.11 Long Compare (CC2541 Only) .............................................................................. 199 22.2 Interrupts ................................................................................................................... 199 22.3 Event Outputs (DMA Trigger and Radio Events) ..................................................................... 200 22.4 Timer Start-and-Stop Synchronization ................................................................................. 200 22.4.1 General........................................................................................................... 200 22.4.2 Timer Synchronous Stop ...................................................................................... 200 22.4.3 Timer Synchronous Start ...................................................................................... 201 22.5 Timer 2 Registers ......................................................................................................... 202 23 CC253x Radio................................................................................................................... 208 23.1 RF Core .................................................................................................................... 209 23.1.1 Interrupts......................................................................................................... 209 23.1.2 Interrupt Registers .............................................................................................. 209 23.2 FIFO Access............................................................................................................... 213 23.3 DMA ........................................................................................................................ 213 23.4 Memory Map .............................................................................................................. 213 23.4.1 RXFIFO .......................................................................................................... 214 23.4.2 TXFIFO........................................................................................................... 214 23.4.3 Frame-Filtering and Source-Matching Memory Map....................................................... 214 23.5 Frequency and Channel Programming ................................................................................ 215 23.6 IEEE 802.15.4-2006 Modulation Format............................................................................... 215 23.7 IEEE 802.15.4-2006 Frame Format .................................................................................... 217 23.7.1 PHY Layer ....................................................................................................... 217 23.7.2 MAC Layer....................................................................................................... 217 23.8 Transmit Mode ............................................................................................................ 218 23.8.1 TX Control ....................................................................................................... 218 23.8.2 TX State Timing................................................................................................. 218 23.8.3 TXFIFO Access ................................................................................................. 218 23.8.4 Retransmission.................................................................................................. 219 23.8.5 Error Conditions................................................................................................. 219 23.8.6 TX Flow Diagram ............................................................................................... 219 23.8.7 Transmitted Frame Processing ............................................................................... 221 23.8.8 Synchronization Header ....................................................................................... 221 23.8.9 Frame-Length Field............................................................................................. 221 23.8.10 Frame Check Sequence ..................................................................................... 221 23.8.11 Interrupts ....................................................................................................... 222 23.8.12 Clear-Channel Assessment.................................................................................. 222 23.8.13 Output Power Programming ................................................................................. 222 23.8.14 Tips and Tricks ................................................................................................ 222 23.9 Receive Mode ............................................................................................................ 222 23.9.1 RX Control ....................................................................................................... 222 23.9.2 RX State Timing ................................................................................................ 223 23.9.3 Received-Frame Processing .................................................................................. 223 23.9.4 Synchronization Header and Frame-Length Fields ........................................................ 224 23.9.5 Frame Filtering .................................................................................................. 224 23.9.6 Source Address Matching ..................................................................................... 227 23.9.7 Frame-Check Sequence ....................................................................................... 230 23.9.8 Acknowledgement Transmission ............................................................................. 230 23.10 RXFIFO Access........................................................................................................... 232 23.10.1 Using the FIFO and FIFOP .................................................................................. 232 23.10.2 Error Conditions ............................................................................................... 233 23.10.3 RSSI ............................................................................................................ 233 23.10.4 Link Quality Indication ........................................................................................ 234 23.11 Radio-Control State Machine ........................................................................................... 234 23.12 Random-Number Generation ........................................................................................... 236 23.13 Packet Sniffing and Radio Test Output Signals ...................................................................... 237 23.14 Command Strobe Processor............................................................................................ 238 23.14.1 Instruction Memory............................................................................................ 238 23.14.2 Data Registers................................................................................................. 239 23.14.3 Program Execution............................................................................................ 239 23.14.4 Interrupt Requests ............................................................................................ 239 23.14.5 Random Number Instruction ................................................................................. 239 23.14.6 Running CSP Programs...................................................................................... 239 23.14.7 Registers ....................................................................................................... 240 23.14.8 Instruction Set Summary ..................................................................................... 241 23.14.9 Instruction Set Definition ..................................................................................... 243 23.15 Registers................................................................................................................... 255 23.15.1 Register Settings Update..................................................................................... 256 23.15.2 Register Access Modes ...................................................................................... 256 23.15.3 Register Descriptions ......................................................................................... 257 24 CC2540 and CC2541 Bluetooth low energy Radio .................................................................. 275 24.1 Registers ................................................................................................................... 276 25 CC2541 Proprietary Mode Radio......................................................................................... 278 25.1 RF Core .................................................................................................................... 279 25.2 Interrupts ................................................................................................................... 279 25.2.1 Interrupt Registers .............................................................................................. 279 25.3 RF Core Data Memory ................................................................................................... 280 25.3.1 FIFOs............................................................................................................. 281 25.3.2 DMA .............................................................................................................. 284 25.3.3 RAM-Based Registers ......................................................................................... 285 25.3.4 Variables in RAM Page 5...................................................................................... 291 25.4 Bit-Stream Processor..................................................................................................... 291 25.4.1 Whitening ........................................................................................................ 291 25.4.2 CC2500-Compatible PN9 Whitening ......................................................................... 292 25.4.3 CRC .............................................................................................................. 293 25.4.4 Coprocessor Mode ............................................................................................. 295 25.5 Frequency and Channel Programming ................................................................................ 296 25.6 Modulation Formats ...................................................................................................... 296 25.7 Receiver.................................................................................................................... 296 25.8 Packet Format............................................................................................................. 297 25.8.1 RX FIFO Packet Organization ................................................................................ 299 25.8.2 TX FIFO Packet Organization................................................................................. 300 25.8.3 TX Buffers for ACK Payload................................................................................... 300 25.9 Link Layer Engine......................................................................................................... 301 25.9.1 Command Register ............................................................................................. 302 25.9.2 Radio Tasks ..................................................................................................... 302 25.9.3 RF Test Commands............................................................................................ 317 25.10 Random Number Generation ........................................................................................... 318 25.11 Packet Sniffing ............................................................................................................ 319 25.12 Registers................................................................................................................... 320 25.12.1 Register Overview............................................................................................. 320 25.12.2 Register Settings Update..................................................................................... 321 25.12.3 SFR Register Descriptions................................................................................... 322 26 Voltage Regulator ............................................................................................................. 342 27 Available Software ............................................................................................................ 343 27.1 SmartRF™ Software for Evaluation (www.ti.com/smartrfstudio) ................................................... 344 27.2 RemoTI™ Network Protocol (www.ti.com/remoti) .................................................................... 344 27.3 SimpliciTI™ Network Protocol (www.ti.com/simpliciti) ............................................................... 345 27.4 TIMAC Software (www.ti.com/timac)................................................................................... 345 27.5 Z-Stack™ Software (www.ti.com/z-stack) ............................................................................. 346 27.6 BLE Stack Software ...................................................................................................... 346 A Abbreviations................................................................................................................... 347 B Additional Information....................................................................................................... 350 B.1 Texas Instruments Low-Power RF Web Site ......................................................................... 351 B.2 Low-Power RF Online Community ..................................................................................... 351 B.3 Texas Instruments Low-Power RF Developer Network.............................................................. 351 B.4 Low-Power RF eNewsletter ............................................................................................. 351 C References....................................................................................................................... 352 Revision History ........................................................................................................................ 353