MA245x_DB-R_v1.02_Spetek.pdf下载

Table of Contents 1 Myriad 2 Platorm...................................................................................................................6 1.1 Overview......................................................................................................................................6 1.2 Hardware Summary.....................................................................................................................7 1.3 IC nomenclature...........................................................................................................................8 2 Top-Level System....................................................................................................................9 2.1 MA245x Bus Interconnect...........................................................................................................9 2.2 Boot Operanon..........................................................................................................................16 2.3 Secure Boot................................................................................................................................46 3 CPU Sub-system....................................................................................................................52 3.1 LEON4 – High-performance SPARC V8 32-bit Processor............................................................52 3.2 GRFPU – High-performance IEEE-754 Floanng-point unit.........................................................74 3.3 DSU4 – LEON4 Hardware Debug Support Unit..........................................................................81 3.4 Leon L2C – Level 2 Cache controller for the Leons....................................................................98 3.5 Interrupt Controller.................................................................................................................114 3.6 Timers......................................................................................................................................123 3.7 Clock, Power and Reset Control...............................................................................................131 3.8 AON block................................................................................................................................159 3.9 Retennon Register...................................................................................................................163 3.10 Temperature Sensors.............................................................................................................166 3.11 USB Controller........................................................................................................................170 3.12 USB PHY.................................................................................................................................424 3.13 Mobile Storage/SDIO.............................................................................................................476 3.14 Gigabit Ethernet Media Access Controller (MAC).................................................................644 3.15 AHB_DMA..............................................................................................................................659 3.16 APB_I2S..................................................................................................................................809 3.17 APB_I2C..................................................................................................................................847 3.18 APB_SPI..................................................................................................................................936 3.19 APB_UART............................................................................................................................1011 3.20 GPIO Interface......................................................................................................................1075 3.21 JTAG Interface......................................................................................................................1097 4 SHAVE Protessor Core.......................................................................................................1099 4.1 Local Address Space Control Unit..........................................................................................1099 4.2 L1 Caches...............................................................................................................................1100 4.3 Translanon Lookaside Bufer..................................................................................................1103 4.4 Interrupt Request Support.....................................................................................................1105 4.5 Register Files..........................................................................................................................1105 4.6 SHAVE Instrucnon Set Architecture.......................................................................................1124 4.7 Register Interface...................................................................................................................1320 4.8 SHAVE Debug & Control Unit (DCU)......................................................................................1326 5 Protessor Memory Blotk (PMB)........................................................................................1347 5.1 CMX Memory System............................................................................................................1347 5.2 CMX FIFO...............................................................................................................................1358 Intel® Movidius™ Confdennal 3 MA245x-DB-1.02 Released to Shanghai Spetek Information Technology Development Co., Ltd. Per Intel CNDA# cnda023213 5.3 CMX DMA Controller.............................................................................................................1364 5.4 Bicubic Filter..........................................................................................................................1387 5.5 Myriad 2 Mutex Controller....................................................................................................1411 5.6 SHAVE L2 Cache.....................................................................................................................1417 6 DRAM Subsystem..............................................................................................................1430 6.1 DDR Controller.......................................................................................................................1430 6.2 DDR PHY.................................................................................................................................1485 7 Media Subsystem (MSS)....................................................................................................1672 7.1 Overview................................................................................................................................1672 7.2 Feature Set.............................................................................................................................1672 7.3 Block diagrams.......................................................................................................................1673 7.4 Architecture...........................................................................................................................1673 7.5 Sofware Driver Notes............................................................................................................1681 7.6 Register Interface...................................................................................................................1688 7.7 Camera Interface...................................................................................................................1703 7.8 LCD Controller / Video Out....................................................................................................1738 7.9 NAL.........................................................................................................................................1793 7.10 MIPI Controller.....................................................................................................................1822 7.11 MIPI D-PHY Bidir 2L..............................................................................................................1889 7.12 Streaming Image Processing Pipeline Accelerators.............................................................1994 7.13 Accelerator Memory Controller...........................................................................................2187 8 Power Management..........................................................................................................2195 8.1 Power Management Features...............................................................................................2195 8.2 Power Island defninons........................................................................................................2197 8.3 Power states...........................................................................................................................2199 8.4 Core voltages.........................................................................................................................2204 8.5 Dynamic Frequency scaling support......................................................................................2204 9 Elettrital...........................................................................................................................2206 9.1 Overview................................................................................................................................2206 9.2 Chip Operanng Condinons.....................................................................................................2206 9.3 GPIO Pins................................................................................................................................2208 9.4 Operanng ranges....................................................................................................................2219 10 Patkage...........................................................................................................................2220 10.1 Overview..............................................................................................................................2220 10.2 Package Thermal Informanon..............................................................................................2222 10.3 Solder Refow Profle...........................................................................................................2222 10.4 Moisture Sensinvity Level (MSL)..........................................................................................2223 10.5 Restricnon On Hazardous Substances (ROHS) compliance.................................................2223 10.6 VFBGA Package Ball out.......................................................................................................2224 10.7 BGA Package Outline...........................................................................................................2225 11 Movidius Produtt Ordering Informaton..........................................................................2226 11.1 Product Ordering Codes......................................................................................................2226 11.2 Product Ordering Opnons....................................................................................................2226 11.3 Minimum Order Requirements...........................................................................................2227 Intel® Movidius™ Confdennal 4 MA245x-DB-1.02 Released to Shanghai Spetek Information Technology Development Co., Ltd. Per Intel CNDA# cnda023213 11.4 MA245x Delivery Tray..........................................................................................................2228