-
superspeed_inter-chip_supplement_1_02_19may2014.pdf下载
资源介绍
1 Introduction..............................................................................................................................................10
1.1 SSIC Significant Features ................................................................................................................11
1.2 SSIC and Standard SuperSpeed Comparison.................................................................................11
1.3 Related Documents ..........................................................................................................................12
1.4 Terminology......................................................................................................................................12
1.5 Acronyms and Terms .......................................................................................................................12
2 Adaptation of M-PHY for the Physical Layer ........................................................................................14
2.1 M-PHY for SSIC Overview ...............................................................................................................14
2.2 M-PHY MODULE Capabilities..........................................................................................................14
2.3 M-PHY Configuration Attributes .......................................................................................................21
2.4 M-PHY State Machine......................................................................................................................22
2.5 LS-MODE Support............................................................................................................................22
3 Link Layer.................................................................................................................................................31
3.1 Bit and Byte Ordering .......................................................................................................................31
3.2 Logical Idle and FLR non-insertion...................................................................................................32
3.3 Line Coding ......................................................................................................................................33
3.4 Clock Compensation ........................................................................................................................34
3.5 Data Scrambling ...............................................................................................................................36
3.6 PowerOn Reset and Inband Reset...................................................................................................37
3.7 Link Layer Timing Requirements......................................................................................................38
3.8 SSIC Link Training and Status State Machine (LTSSM)..................................................................39
4 Protocol Layer..........................................................................................................................................51
4.1 Port Capability Link Management Packet (LMP) .............................................................................51
4.2 Timing Parameters ...........................................................................................................................51
5 Device Framework...................................................................................................................................53
5.1 Dynamic Attachment and Removal ..................................................................................................53
6 MPHY.TEST ..............................................................................................................................................55
6.1 Overview...........................................................................................................................................55
6.2 Entering MPHY.TEST.......................................................................................................................56
6.3 Loopback Testing .............................................................................................................................57
6.4 Receive Burst Testing ......................................................................................................................58
6.5 Tx Compliance Mode........................................................................................................................58
6.6 Analog Loopback Mode....................................................................................................................58
6.7 MPHY.TEST Block Registers...........................................................................................................59
7 Timing Diagrams Appendix (Informative) .........................................