P2020EC.pdf下载

The following list provides an overview of the P2020 feature set: • Dual high-performance Power Architecture® e500 cores. • 36-bit physical addressing – Double-precision floating-point support – 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache for each core – 800-MHz to 1.2-GHz clock frequency • 512 Kbyte L2 cache with ECC. Also configurable as SRAM and stashing memory. • Three 10/100/1000 Mbps enhanced three-speed Ethernet controllers (eTSECs) – TCP/IP acceleration, quality of service, and classification capabilities – IEEE Std 1588™ support – Lossless flow control – R/G/MII, R/TBI, SGMII • High-speed interfaces supporting various multiplexing options: – Four SerDes to 3.125 GHz multiplexed across controllers – Three PCI Express interfaces – Two Serial RapidIO interfaces – Two SGMII interfaces • High-Speed USB controller (USB 2.0) – Host and device support – Enhanced host controller interface (EHCI) – ULPI interface to PHY • Enhanced secure digital host controller (SD/MMC) Enhanced Serial peripheral interface (eSPI) • Integrated security engine – Protocol support includes SNOW, ARC4, 3DES, AES, RSA/ECC, RNG, single-pass SSL/TLS, Kasumi – XOR acceleration • 64-bit DDR2/DDR3 SDRAM memory controller with ECC support