Xilinx的去隔行代码及其相关注释

Xilinx的去隔行代码和注释 module deint_v2mult_4L ( rst, // resets input data register and control clk, // video component rate clock, 27Mhz for SDTV Fi, // Low to High signals start of Field One Vi, // High signals Vertical Blanking Hi, // High signals Horizontal Blanking Fo, // Field signal delayed by pipe length Vo, // Vertical signal delayed by pipe length Ho, // Horizontal signal delayed by pipe length cei, // input component rate is 1/2 the clock rate ceo, // output component rate is 1/2 the clock rate R_in, // video component in, I[8].F[2], twos complement G_in, // video component in, I[8].F[2], twos complement B_in, // video component in, I[8].F[2], twos complement R_out_real, // video component out, I[8].F[2], twos complement, clamped G_out_real, // video component out, I[8].F[2], twos complement, clamped B_out_real, // video component out, I[8].F[2], twos complement, clamped R_out_filt, // video component out, I[8].F[2], twos complement, clamped G_out_filt, // video component out, I[8].F[2], twos complement, clamped B_out_filt, // video component out, I[8].F[2], twos complement, clamped );