Easily-Integrated and Energy-Efficient Design Techniques for SAR ADC下载

Abstract: This dissertation presents four circuit design techniques for successive-approximation register (SAR) analog-to-digital converters (ADCs). According to the measurement results of the proof-of-concept prototypes, the proposed techniques are able to reduce the design overhead of the front-end and reference buffer and improve the ADC performance. The proposed techniques and their associated chip measurement results are sketched as follows: The first technique is to develop a low input capacitance architecture for SAR ADCs. A 10-bit prototype is fabricated in 0.13-μm CMOS process. Compared with conventional successive approximation ADCs, the proposed ADC can reduce the input capacitance to 1.2 pF for 10-bit resolution. At 12 MS/s and 1.2-V supply, this ADC consumes 0.32 mW and achieves an SNDR of 50.89 dB, resulting in a figure of merit (FOM) of 95 fJ/conversion-step.